1. Field of the Invention
The present invention relates to methods of fabricating field emission arrays including planarized grids. Particularly, the present invention relates to field emission array fabrication methods that facilitate optimization of the size of grid openings above each of the emitter tips thereof. The present invention also relates to field emission arrays fabricated in accordance with the method of the present invention.
2. Background of Related Art
Typically, field emission displays (“FEDs”) include an array of pixels, each of which includes one or more substantially conical emitter tips. The array of pixels of a field emission display is typically referred to as a field emission array. Each of the emitter tips is electrically connected to a negative voltage source by means of a cathode conductor line, which is also typically referred to as a column line.
Another set of electrically conductive lines, which are typically referred to as row lines or as gate lines, extends over the pixels of the field emission array. Row lines typically extend across a field emission display substantially perpendicularly to the direction in which the column lines extend. Accordingly, the paths of a row line and of a column line typically cross proximate (e.g., above and below, respectively) the location of an emitter tip. The row lines of a field emission array are electrically connected to a relatively positive voltage source. Thus, as a voltage is applied across the column line and the row line, electrons are emitted by the emitter tips and accelerated through an opening in the row line.
As electrons are emitted by emitter tips and accelerate past the row line that extends over the pixel, the electrons are directed toward a corresponding pixel of a relatively positively charged electro-luminescent panel of the field emission display, which is spaced apart from and substantially parallel to the field emission array. As electrons impact a pixel of the electro luminescent panel, the pixel is illuminated. The degree to which the pixel is illuminated depends upon the number of electrons that impact the pixel.
An exemplary method of fabricating field emission arrays is taught in U.S. Pat. No. 5,372,973 (hereinafter “the '973 Patent”), issued to Trung T. Doan et al. on Dec. 13, 1994. The field emission array fabrication method of the '973 Patent includes an electrically conductive grid, or gate, disposed over the surface thereof and including apertures substantially above each of the emitter tips of the field emission array. While the electrically conductive grid of the field emission array disclosed in the '973 Patent is fabricated from an electrically conductive material such as chromium, field emission arrays that include grids of semiconductive material, such as silicon, are also known. Known processes, including chemical mechanical planarization (“CMP”) and a subsequent mask and etch, are employed to provide a substantially planar grid surface and to define grid openings or apertures therethrough, which are positioned above each of the emitter tips.
The process of the '973 Patent is, however, somewhat undesirable in that upon optimization of either the thickness of the dielectric layer or the diameters of the grid openings, the other may not be optimized. Moreover, as the process of the '973 Patent employs layers of dielectric material that are subsequently covered by a grid material without any intervening process steps (e.g., planarization of any imperfections and disposal of another layer of dielectric material thereover), electrically conductive imperfections that may extend through the dielectric material from the substrate to the grid are typically not removed by intervening process steps.
Accordingly, there is a need for a field emission array fabrication process that facilitates optimization of both the diameter of grid openings and the thickness of the dielectric layer thereof. There is also a need for a field emission array fabrication process that reduces the incidence of electrically conductive imperfections that extend from the substrate to the grid and that,thereby, reduces the likelihood of electrical shorts during use of the field emission array.